1. Field of the Invention
The present invention relates to a solid-state imaging device, typified by a CMOS image sensor, a control method therefor, and a camera system.
2. Description of the Related Art
There has been proposed a CMOS image sensor that has a pixel array section having a plurality of pixels arranged two-dimensionally, reads pixel signals, read from the individual pixels in the pixel array section, sequentially pixel column by pixel column, performs CDS (Correlated Double Sampling) or the like on each column of pixel signals to convert the pixel signals to image signals to be output.
The main stream of CMOS image sensors is of a column parallel output type which has an FD (Floating Diffusion) amplifier having an FD for each pixel, selects one row of pixels in the pixel array, and simultaneously reads pixel signals in the row in the column direction.
This is because the FD amplifiers disposed in the pixels are difficult to provide a sufficient drive performance, so that the data rate needs to be reduced, which makes the parallel processing advantageous.
Various pixel signal reading (outputting) circuits have been proposed for column parallel output type CMOS image sensors.
The most advanced type in the reading circuits has an analog-digital converter (hereinafter abbreviated as “ADC”) provided for each column to acquire a pixel signal as a digital signal.
A CMOS image sensor having a column parallel ADC mounted thereon is disclosed in, for example, W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999 (Non-patent Document 1) and JP-A-2005-278135 (Patent Document 1).
It is known that when very intense light like sunlight is input to such a CMOS image sensor, the signal level at the input portion drops, causing a blackening phenomenon in which even the light is very bright, an image appears black.
The CMOS image sensor is provided with some correction means to avoid this phenomenon (see, for example, JP-A-2008-283557 (Patent Document 2)).
As an approach to prevent a blackening phenomenon, there has been proposed a method in which an amplifier with no photodiode (hereinafter referred to as “pixel dummy amplification transistor”) is provided in a pixel at the time of detecting a blackening phenomenon, and a reset voltage output from a pixel is replaced with the output voltage of the pixel dummy amplification transistor.
This method is disclosed in, for example, JP-A-2000-287131 (Patent Document 3).
Another method has also been proposed which uses a plurality of supply voltages in the pixel section according to different purposes, such as increasing the operational margin of the pixel section and complete transfer of signal charges (see, for example, WO03/085964 (Patent Document 4)).
FIG. 1 is a circuit diagram showing the general configuration of a solid-state imaging device (CMOS image sensor) to which the proposed techniques are adapted.
A solid-state imaging device 1 includes a pixel section 2, a vertical scan section 3, a horizontal scan section 4, and a column processing circuit group 5 having ADCs as shown in FIG. 1.
The solid-state imaging device 1 further includes a digital-analog converter (hereinafter abbreviated as “DAC”) 6, a correction bias circuit 7, a communication timing control section 8, a digital operation section 9, and an output section 10.
The valid pixel region of the pixel section 2 has a two-dimensional array of unit pixels 21, each column having a pixel dummy section 22 including a pixel dummy amplification transistor.
The unit pixel 21 has a photodiode PD21 which is a photoelectric converting element. The unit pixel 21 further includes a total of four transistors, namely, a transfer transistor T21, a reset transistor T22, an amplification transistor T23, and a selection transistor T24.
A transfer pulse TRG, a reset pulse RST, a selection pulse SEL, etc. are supplied to the respective pixel transistors from the vertical scan section 3 to convert signal charges, obtained by the photodiode PD21, to a pixel signal SIG, which is in turn output to a vertical signal line 23.
The pixel dummy section 22 includes a pixel dummy amplification transistor DT and a pixel dummy selection transistor ST. The pixel dummy section 22 is controlled by a selection pulse DSEL from the vertical scan section 3, and a clamp voltage SLP_SUN from a blackening correction bias circuit.
Although the unit pixel part is configured to include four transistors in the above description, it may have another configuration having, for example, three transistors excluding the selection transistor. It is desirable that the pixel dummy section 22 has the same configuration as that of the unit pixel part.
FIGS. 2A and 2B are diagrams for explaining an operation and AD conversion for a row of pixels to be read when the amount of light is normal and when the light is very intense to cause a blackening phenomenon.
An output at the time of the normal amount of light shown in FIG. 2A is given by the difference between a count value in a period A where a pixel signal SIG becomes identical to a reference signal SLP_ADC for AD conversion in a P-phase period and a count value in a period B where a pixel signal SIG becomes identical to the reference signal SLP_ADC for AD conversion in a D-phase period.
On the other hand, an output at the time of the very intense amount of light which causes a blackening phenomenon shown in FIG. 2B is clamped so that the pixel signal SIG is not made equal to or lower than a set voltage by a clamp voltage SLP_SUN from blackening correction bias circuit.
Accordingly, the pixel signal SIG does not become identical to the reference signal SLP_ADC for AD conversion in the P-phase period as seen in a period C.
When the pixel signal SIG does not become identical to the reference signal SLP_ADC for AD conversion in the P-phase period, it is determined that a blackening phenomenon has occurred, and the count value is counted fully, or the blackening phenomenon is corrected by performing an operation such as replacing the count value with a fixed count value that is equal to or greater than a saturation signal. It is to be noted however that the clamp voltage SLP_SUN from the blackening correction bias circuit needs to be set properly. When the set value is improper, the blackening phenomenon cannot be corrected, or the correction may be executed improperly to degrade the output characteristic at the normal time.